TM 11-6625-3081-23
1-24. TEST CONSOLE TEST BENCH 2A2 (cont)
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(2) Control Signals.
Control signals from the switch controller assembly are
routed through the rear panel board and the motherboards to the quadrant control
CCAs.
The relay control signals generated by each of the quadrant control CCAs are
routed through the motherboards to 16 matrix relay CCAs in each quadrant.
Control
signals are used to select the CCA and the relay and to control the relay. There are
30 signal relays on each of the quadrants’ 16 matrix relay CCAs. The signal relays
are controlled from the switch controller assembly in groups of 30, each relay corre-
sponds to one UUT pin; UUT pins 1 thru 30 are in quadrant 1, 31 thru 60 in quadrant 2,
61 thru 90 in quadrant 3, and 91 thru 120 in quadrant 4.
(3) Matrix Inputs.
The 16 matrix input connectors located on the matrix switch
assembly rear panel are used as input/output ports to the external stimulus/
measurement instruments.
The connectors are numbered from 1 thru 16 corresponding to
the matrix relay CCAs in each quadrant.
Any one of 16 stimulus input signals can be
sent to any of the 120 UUT pins.
Any signal from the UUT can be sent to any of the
instruments connected to the matrix switch assembly.
k.
SWITCH CONTROLLER ASSEMBLY 2A2A12
(1) General.
The switch controller assembly 2A2A12 (FO-29) controls the matrix
switch asssembly 2A2A10 by translating computer command messages, present on the IEEE
488 bus, into command and timing signals.
(2) Microprocessor and Associated Circuits.
The switch controller assembly is a
microprocessor- driven instrument.
The microprocessor control circuits are comprised
of the microprocessor, the control decoder, and the clock circuit. These circuits, in
conjunction with the IEEE 488 bus handshake circuit and the interrupt gating circuits,
process all commands received from the IEEE 488 bus. They perform all of the func-
tions necessary to control the matrix switch assembly.
(3) Bus Architecture.
The switch controller assembly circuitry is implemented
using bus architecture.
The major buses contained in the switch controller are:
Main Data Bus (8 bits) is used to transmit data bidirectionally between
the microprocessor circuits and the interface circuits.
Control Bus (8 bits) is used to transmit data bidirectionally between the
microprocessor circuits and the interface circuits for the control lines.
Processor Bus (8 bits) connects the main data bus to the microprocessor
via the main data bus switch driver circuits.
Because this bus also
connects to each of the ROMs that comprise the memory of the unit, the
data output from any enabled ROM is fed by this bus to the
microprocessor.
ROM Address Bus (9 bits) transmits address information from the
microprocessor to the ROMs.
Control-Decoder Bus consists of the four, device-select control bits from
the microprocessor.
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